Layout-aware Low Power Test Pattern Generation
نویسندگان
چکیده
A new test pattern generation method for low power test is presented. The proposed method is based on the scan chain configuration after Place and Route (P&R) process. It is also based on the Weighted Transition Metric(WTM) for low power test pattern generation. It does not need to modify any design process and very easy to run. The experimental results of ISCAS 89’ benchmark circuits show the effectiveness of proposed method. Using this method, routing area of scan chain routing is optimized and the power consumption is dramatically reduced.
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